-- indi16 vhdl -- Component Declarations -- (C)2007 K Ring Technologies Semiconductor -- designed for 66MHz operation LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; PACKAGE system IS COMPONENT ufm PORT ( -- Slave WISHBONE Classic interface (STB_I decoded) RST_I : IN STD_LOGIC; CLK_I : IN STD_LOGIC; ADR_I : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DAT_I : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DAT_O : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); WE_I : IN STD_LOGIC; SEL_I : IN STD_LOGIC; STB_I : IN STD_LOGIC; ACK_O : OUT STD_LOGIC; CYC_I : IN STD_LOGIC; -- 3.33MHz OSC out WDT_O : OUT STD_LOGIC ); END COMPONENT; COMPONENT ports PORT ( -- Slave WISHBONE Classic interface (STB_I decoded) HLT_I : IN STD_LOGIC; RST_I : IN STD_LOGIC; CLK_I : IN STD_LOGIC; ADR_I : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DAT_I : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DAT_O : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); WE_I : IN STD_LOGIC; SEL_I : IN STD_LOGIC; STB_I : IN STD_LOGIC; ACK_O : OUT STD_LOGIC; CYC_I : IN STD_LOGIC; -- Input port PORT_I : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- Output port (tristateable) PORT_O : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; COMPONENT ata PORT ( -- Slave WISHBONE Classic interface (STB_I decoded) HLT_I : IN STD_LOGIC; RST_I : IN STD_LOGIC; CLK_I : IN STD_LOGIC; ADR_I : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DAT_I : IN STD_LOGIC_VECTOR(15 DOWNTO 0); DAT_O : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); WE_I : IN STD_LOGIC; SEL_I : IN STD_LOGIC; STB_I : IN STD_LOGIC; ACK_O : OUT STD_LOGIC; CYC_I : IN STD_LOGIC; -- ATA Interface RESETN : OUT STD_LOGIC; DD : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); DMARQ : IN STD_LOGIC; --DMA Request DIOWN : OUT STD_LOGIC; DIORN : OUT STD_LOGIC; IORDY : IN STD_LOGIC; CSEL : OUT STD_LOGIC; -- Cable Select DMACKN : OUT STD_LOGIC; -- DMA ACK INTRQ : IN STD_LOGIC; -- Interrupt Request DA : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); CSN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); DASPN : IN STD_LOGIC -- device active/slave present ); END COMPONENT; END system;