-- indi16 vhdl
-- Register Prepost Unit
-- (C)2007 K Ring Technologies Semiconductor
-- designed for 66MHz operation

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY regs IS
	PORT
	(
		DAT_O					: OUT	STD_LOGIC_VECTOR(15 DOWNTO 0);
		DAT_I					: IN	STD_LOGIC_VECTOR(15 DOWNTO 0);
		CLK_I, WE_I, HLT_I		: IN	STD_LOGIC;
		SD, DRT, RST_I			: IN	STD_LOGIC;
		REG						: IN	STD_LOGIC_VECTOR(1 DOWNTO 0)
	);
END regs;

ARCHITECTURE a OF Regs IS
	SIGNAL P, Q, R, S		: STD_LOGIC_VECTOR(15 DOWNTO 0);
	-- refresh register
	SIGNAL REF				: STD_LOGIC_VECTOR(7 DOWNTO 0);
	CONSTANT Zero16 		: STD_LOGIC_VECTOR(15 DOWNTO 0) := "0000000000000000";
BEGIN
	PROCESS(SD, DRT, REG)
		VARIABLE RVal		: STD_LOGIC_VECTOR(15 DOWNTO 0);
	BEGIN
		CASE REG IS
			WHEN "00" =>
				RVal := P;
			WHEN "01" =>
				RVal := Q;
			WHEN "10" =>
				RVal := R;
			WHEN "11" =>
				RVal := S;
			END CASE;
		IF DRT = '0' AND SD = '0' THEN
			IF REG = "00" THEN
				-- P register indirect store
				-- DAT_O routed to address bus
				DAT_O <= REF & REF;
				REF <= REF + 1;
			ELSE
				DAT_O <= RVal - 1;
			END IF;
		ELSE
			DAT_O <= RVal;
		END IF;	
	END PROCESS;
	PROCESS(CLK_I, RST_I)
		VARIABLE RVal		: STD_LOGIC_VECTOR(15 DOWNTO 0);
	BEGIN
		IF RST_I = '1' THEN
			-- Reset happening
			P <= Zero16;
			Q <= Zero16;
			R <= Zero16;
			S <= Zero16;
		ELSIF rising_edge(CLK_I) AND WE_I = '1' AND HLT_I = '0' THEN
			IF DRT = '0' AND SD = '1' THEN
				RVal := DAT_I + 1;
			ELSE
				RVal := DAT_I;
			END IF;
			CASE REG IS
				WHEN "00" =>
					IF DRT = '1' THEN
						P <= RVal;
					END IF;
				WHEN "01" =>
					Q <= RVal;
				WHEN "10" =>
					R <= RVal;
				WHEN "11" =>
					S <= RVal;
			END CASE;
		END IF;
	END PROCESS;
END a;