-- indi16 vhdl
-- 16 bit data port (I and O)
-- (C)2007 K Ring Technologies Semiconductor
-- designed for 66MHz operation

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY ports IS
	PORT
	(
		-- Slave WISHBONE Classic interface (STB_I decoded)
		HLT_I	: IN	STD_LOGIC;
		RST_I	: IN	STD_LOGIC;
		CLK_I	: IN	STD_LOGIC;
		ADR_I	: IN	STD_LOGIC_VECTOR(15 DOWNTO 0);
		DAT_I	: IN	STD_LOGIC_VECTOR(15 DOWNTO 0);
		DAT_O	: OUT	STD_LOGIC_VECTOR(15 DOWNTO 0);
		WE_I	: IN	STD_LOGIC;
		SEL_I	: IN	STD_LOGIC;
		STB_I	: IN	STD_LOGIC;
		ACK_O	: OUT	STD_LOGIC;
		CYC_I	: IN	STD_LOGIC;
		
		-- Input port
		PORT_I	: IN	STD_LOGIC_VECTOR(15 DOWNTO 0);
		-- Output port (tristateable)
		PORT_O	: INOUT	STD_LOGIC_VECTOR(15 DOWNTO 0)
	);
END ports;

ARCHITECTURE a OF ports IS
	SIGNAL Zero16 	: STD_LOGIC_VECTOR(15 DOWNTO 0) := "0000000000000000";
	SIGNAL Hold, Tri: STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
	PROCESS(CLK_I, RST_I)
	BEGIN
		IF RST_I = '1' THEN
			Tri <= Zero16;
			Hold <= Zero16;
		ELSIF rising_edge(CLK_I) AND STB_I = '1' AND HLT_I = '0' THEN
			IF WE_I = '1' THEN
				IF ADR_I(0) = '1' THEN
					-- tristate output port select
					Tri <= DAT_I;
				ELSE
					-- output port
					Hold <= DAT_I;
				END IF;
			END IF;
		END IF;
	END PROCESS;
	ACK_O <= STB_I;
	-- do tristate outputs
	buff: FOR i IN 15 DOWNTO 0 GENERATE
		PROCESS(Tri)
		BEGIN
			IF Tri(i) = '0' THEN
				PORT_O(i) <= 'Z';
			ELSE
				PORT_O(i) <= Hold(i);
			END IF;
		END PROCESS;
	END GENERATE;
	PROCESS(ADR_I)
	BEGIN
		IF ADR_I(0) = '1' THEN
			-- input port read
			DAT_O <= PORT_I;
		ELSE
			-- read output hold latch
			DAT_O <= Hold;
		END IF;
	END PROCESS;
END a;