Analysis & Synthesis report for indi16 Wed Aug 22 00:00:59 2007 Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Analysis & Synthesis Source Files Read 5. Analysis & Synthesis Resource Usage Summary 6. Analysis & Synthesis Resource Utilization by Entity 7. General Register Statistics 8. Inverted Register Statistics 9. Multiplexer Restructuring Statistics (Restructuring Performed) 10. Source assignments for Top-level Entity: |ata 11. Analysis & Synthesis Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2006 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +----------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +-----------------------------+----------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Wed Aug 22 00:00:59 2007 ; ; Quartus II Version ; 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition ; ; Revision Name ; indi16 ; ; Top-level Entity Name ; ata ; ; Family ; MAX II ; ; Total logic elements ; 79 ; ; Total pins ; 86 ; ; Total virtual pins ; 0 ; ; UFM blocks ; 0 ; +-----------------------------+----------------------------------------------+ +---------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +--------------------------------------------------------------------+---------------+--------------------+ ; Option ; Setting ; Default Value ; +--------------------------------------------------------------------+---------------+--------------------+ ; Device ; EPM1270F256C5 ; ; ; Top-level entity name ; ata ; indi16 ; ; Family name ; MAX II ; Stratix ; ; Use smart compilation ; On ; Off ; ; Restructure Multiplexers ; On ; Auto ; ; State Machine Processing ; Minimal Bits ; Auto ; ; PowerPlay Power Optimization ; Extra effort ; Normal compilation ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Disable OpenCore Plus hardware evaluation ; Off ; Off ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL93 ; VHDL93 ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique -- MAX II ; Balanced ; Balanced ; ; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Remove Duplicate Logic ; On ; On ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Perform gate-level register retiming ; Off ; Off ; ; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ; ; Auto Shift Register Replacement ; On ; On ; ; Auto Clock Enable Replacement ; On ; On ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Auto RAM Block Balancing ; On ; On ; ; Auto Resource Sharing ; Off ; Off ; ; Maximum Number of M512 Memory Blocks ; Unlimited ; Unlimited ; ; Maximum Number of M4K Memory Blocks ; Unlimited ; Unlimited ; ; Maximum Number of M-RAM Memory Blocks ; Unlimited ; Unlimited ; ; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ; ; Show Parameter Settings Tables in Synthesis Report ; On ; On ; ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; ; Retiming Meta-Stability Register Sequence Length ; 2 ; 2 ; ; HDL message level ; Level2 ; Level2 ; +--------------------------------------------------------------------+---------------+--------------------+ +------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +----------------------------------+-----------------+-----------------+-------------------------------------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; +----------------------------------+-----------------+-----------------+-------------------------------------+ ; ata.vhd ; yes ; User VHDL File ; D:/altera/quartus60/indi16v/ata.vhd ; +----------------------------------+-----------------+-----------------+-------------------------------------+ +-----------------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +---------------------------------------------+-------+ ; Resource ; Usage ; +---------------------------------------------+-------+ ; Total logic elements ; 79 ; ; -- Combinational with no register ; 12 ; ; -- Register only ; 60 ; ; -- Combinational with a register ; 7 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 11 ; ; -- 3 input functions ; 3 ; ; -- 2 input functions ; 4 ; ; -- 1 input functions ; 0 ; ; -- 0 input functions ; 1 ; ; -- Combinational cells for routing ; 0 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 79 ; ; -- arithmetic mode ; 0 ; ; -- qfbk mode ; 0 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 0 ; ; -- asynchronous clear/load mode ; 8 ; ; ; ; ; Total registers ; 67 ; ; I/O pins ; 86 ; ; Maximum fan-out node ; CLK_I ; ; Maximum fan-out ; 67 ; ; Total fan-out ; 315 ; ; Average fan-out ; 1.91 ; +---------------------------------------------+-------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Utilization by Entity ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+ ; |ata ; 79 (79) ; 67 ; 0 ; 86 ; 0 ; 12 (12) ; 60 (60) ; 7 (7) ; 0 (0) ; 0 (0) ; |ata ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ ; Total registers ; 67 ; ; Number of registers using Synchronous Clear ; 0 ; ; Number of registers using Synchronous Load ; 0 ; ; Number of registers using Asynchronous Clear ; 8 ; ; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Clock Enable ; 62 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ +--------------------------------------------------+ ; Inverted Register Statistics ; +----------------------------------------+---------+ ; Inverted Register ; Fan out ; +----------------------------------------+---------+ ; DIOWN~reg0 ; 2 ; ; Total number of inverted registers = 1 ; ; +----------------------------------------+---------+ +------------------------------------------------------------------------------------------------------------------------------------------+ ; Multiplexer Restructuring Statistics (Restructuring Performed) ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ ; 3:1 ; 16 bits ; 32 LEs ; 0 LEs ; 32 LEs ; Yes ; |ata|Read[10] ; ; 8:1 ; 2 bits ; 10 LEs ; 8 LEs ; 2 LEs ; Yes ; |ata|Seq[0] ; ; 1:1 ; 16 bits ; 0 LEs ; 0 LEs ; 0 LEs ; Yes ; |ata|DD[12]~reg0 ; +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +-----------------------------------------------+ ; Source assignments for Top-level Entity: |ata ; +----------------+-------+------+---------------+ ; Assignment ; Value ; From ; To ; +----------------+-------+------+---------------+ ; POWER_UP_LEVEL ; Low ; - ; DD[0]~en ; ; POWER_UP_LEVEL ; Low ; - ; DD[1]~en ; ; POWER_UP_LEVEL ; Low ; - ; DD[2]~en ; ; POWER_UP_LEVEL ; Low ; - ; DD[3]~en ; ; POWER_UP_LEVEL ; Low ; - ; DD[4]~en ; ; POWER_UP_LEVEL ; Low ; - ; DD[5]~en ; ; POWER_UP_LEVEL ; Low ; - ; DD[6]~en ; ; POWER_UP_LEVEL ; Low ; - ; DD[7]~en ; ; POWER_UP_LEVEL ; Low ; - ; DD[8]~en ; ; POWER_UP_LEVEL ; Low ; - ; DD[9]~en ; ; POWER_UP_LEVEL ; Low ; - ; DD[10]~en ; ; POWER_UP_LEVEL ; Low ; - ; DD[11]~en ; ; POWER_UP_LEVEL ; Low ; - ; DD[12]~en ; ; POWER_UP_LEVEL ; Low ; - ; DD[13]~en ; ; POWER_UP_LEVEL ; Low ; - ; DD[14]~en ; ; POWER_UP_LEVEL ; Low ; - ; DD[15]~en ; +----------------+-------+------+---------------+ +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition Info: Processing started: Wed Aug 22 00:00:49 2007 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off indi16 -c indi16 Info: Found 2 design units, including 1 entities, in source file clkpal.vhd Info: Found design unit 1: clkpal-a Info: Found entity 1: clkpal Info: Found 2 design units, including 1 entities, in source file dac.vhd Info: Found design unit 1: dac-a Info: Found entity 1: dac Info: Found 2 design units, including 1 entities, in source file dac2.vhd Info: Found design unit 1: dac2-a Info: Found entity 1: dac2 Info: Found 2 design units, including 1 entities, in source file alu.vhd Info: Found design unit 1: alu-a Info: Found entity 1: alu Info: Found 2 design units, including 1 entities, in source file regs.vhd Info: Found design unit 1: Regs-a Info: Found entity 1: regs Info: Found 2 design units, including 1 entities, in source file ufm.vhd Info: Found design unit 1: ufm-a Info: Found entity 1: ufm Info: Found 1 design units, including 0 entities, in source file indi.comp.vhd Info: Found design unit 1: indi Info: Found 1 design units, including 0 entities, in source file system.comp.vhd Info: Found design unit 1: system Info: Found 2 design units, including 1 entities, in source file memdrv.vhd Info: Found design unit 1: memdrv-a Info: Found entity 1: memdrv Info: Found 2 design units, including 1 entities, in source file board.vhd Info: Found design unit 1: board-a Info: Found entity 1: board Info: Found 2 design units, including 1 entities, in source file ports.vhd Info: Found design unit 1: ports-a Info: Found entity 1: ports Info: Found 2 design units, including 1 entities, in source file ata.vhd Info: Found design unit 1: ata-a Info: Found entity 1: ata Info: Elaborating entity "ata" for the top level hierarchy Warning (10034): Output port "CSEL" at ata.vhd(42) has no driver Info: Duplicate registers merged to single register Info: Duplicate register "DD[1]~en" merged to single register "DD[0]~en" Info: Duplicate register "DD[2]~en" merged to single register "DD[0]~en" Info: Duplicate register "DD[3]~en" merged to single register "DD[0]~en" Info: Duplicate register "DD[4]~en" merged to single register "DD[0]~en" Info: Duplicate register "DD[5]~en" merged to single register "DD[0]~en" Info: Duplicate register "DD[6]~en" merged to single register "DD[0]~en" Info: Duplicate register "DD[7]~en" merged to single register "DD[0]~en" Info: Duplicate register "DD[8]~en" merged to single register "DD[0]~en" Info: Duplicate register "DD[9]~en" merged to single register "DD[0]~en" Info: Duplicate register "DD[10]~en" merged to single register "DD[0]~en" Info: Duplicate register "DD[11]~en" merged to single register "DD[0]~en" Info: Duplicate register "DD[12]~en" merged to single register "DD[0]~en" Info: Duplicate register "DD[13]~en" merged to single register "DD[0]~en" Info: Duplicate register "DD[14]~en" merged to single register "DD[0]~en" Info: Duplicate register "DD[15]~en" merged to single register "DD[0]~en" Warning: Output pins are stuck at VCC or GND Warning: Pin "CSEL" stuck at GND Warning: Pin "DMACKN" stuck at VCC Info: Registers with preset signals will power-up high Warning: Design contains 16 input pin(s) that do not drive logic Warning: No output dependent on input pin "ADR_I[5]" Warning: No output dependent on input pin "ADR_I[6]" Warning: No output dependent on input pin "ADR_I[7]" Warning: No output dependent on input pin "ADR_I[8]" Warning: No output dependent on input pin "ADR_I[9]" Warning: No output dependent on input pin "ADR_I[10]" Warning: No output dependent on input pin "ADR_I[11]" Warning: No output dependent on input pin "ADR_I[12]" Warning: No output dependent on input pin "ADR_I[13]" Warning: No output dependent on input pin "ADR_I[14]" Warning: No output dependent on input pin "ADR_I[15]" Warning: No output dependent on input pin "SEL_I" Warning: No output dependent on input pin "CYC_I" Warning: No output dependent on input pin "DMARQ" Warning: No output dependent on input pin "INTRQ" Warning: No output dependent on input pin "DASPN" Info: Implemented 165 device resources after synthesis - the final resource count might be different Info: Implemented 43 input pins Info: Implemented 27 output pins Info: Implemented 16 bidirectional pins Info: Implemented 79 logic cells Info: Quartus II Analysis & Synthesis was successful. 0 errors, 21 warnings Info: Processing ended: Wed Aug 22 00:00:59 2007 Info: Elapsed time: 00:00:11