Fitter report for indi16 Wed Aug 22 00:01:24 2007 Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Fitter Summary 3. Fitter Settings 4. Pin-Out File 5. Fitter Resource Usage Summary 6. Input Pins 7. Output Pins 8. Bidir Pins 9. I/O Bank Usage 10. All Package Pins 11. Output Pin Default Load For Reported TCO 12. Fitter Resource Utilization by Entity 13. Delay Chain Summary 14. Control Signals 15. Global & Other Fast Signals 16. Non-Global High Fan-Out Signals 17. Interconnect Usage Summary 18. LAB Logic Elements 19. LAB-wide Signals 20. LAB Signals Sourced 21. LAB Signals Sourced Out 22. LAB Distinct Inputs 23. Fitter Device Options 24. Advanced Data - General 25. Advanced Data - Placement Preparation 26. Advanced Data - Placement 27. Advanced Data - Routing 28. Fitter Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2006 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +----------------------------------------------------------------------+ ; Fitter Summary ; +-----------------------+----------------------------------------------+ ; Fitter Status ; Successful - Wed Aug 22 00:01:23 2007 ; ; Quartus II Version ; 6.0 Build 202 06/20/2006 SP 1 SJ Web Edition ; ; Revision Name ; indi16 ; ; Top-level Entity Name ; ata ; ; Family ; MAX II ; ; Device ; EPM1270F256C5 ; ; Timing Models ; Final ; ; Total logic elements ; 77 / 1,270 ( 6 % ) ; ; Total pins ; 86 / 212 ( 41 % ) ; ; Total virtual pins ; 0 ; ; UFM blocks ; 0 / 1 ( 0 % ) ; +-----------------------+----------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------+ ; Fitter Settings ; +--------------------------------------------------------+--------------------------------+--------------------------------+ ; Option ; Setting ; Default Value ; +--------------------------------------------------------+--------------------------------+--------------------------------+ ; Device ; EPM1270F256C5 ; ; ; Use smart compilation ; On ; Off ; ; PowerPlay Power Optimization ; Extra effort ; Normal compilation ; ; Fitter Effort ; Standard Fit ; Auto Fit ; ; Router Timing Optimization Level ; Normal ; Normal ; ; Placement Effort Multiplier ; 1.0 ; 1.0 ; ; Router Effort Multiplier ; 1.0 ; 1.0 ; ; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; ; Optimize Fast-Corner Timing ; Off ; Off ; ; Guarantee I/O Paths Have Zero Hold Time at Fast Corner ; On ; On ; ; Optimize Timing ; Normal compilation ; Normal compilation ; ; Optimize IOC Register Placement for Timing ; On ; On ; ; Limit to One Fitting Attempt ; Off ; Off ; ; Final Placement Optimizations ; Automatically ; Automatically ; ; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; ; Fitter Initial Placement Seed ; 1 ; 1 ; ; Slow Slew Rate ; Off ; Off ; ; PCI I/O ; Off ; Off ; ; Weak Pull-Up Resistor ; Off ; Off ; ; Enable Bus-Hold Circuitry ; Off ; Off ; ; Auto Delay Chains ; On ; On ; ; Perform Physical Synthesis for Combinational Logic ; Off ; Off ; ; Perform Register Duplication ; Off ; Off ; ; Perform Register Retiming ; Off ; Off ; ; Perform Asynchronous Signal Pipelining ; Off ; Off ; ; Physical Synthesis Effort Level ; Normal ; Normal ; ; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; ; Auto Register Duplication ; Auto ; Auto ; ; Auto Global Clock ; On ; On ; ; Auto Global Register Control Signals ; On ; On ; ; Always Enable Input Buffers ; Off ; Off ; +--------------------------------------------------------+--------------------------------+--------------------------------+ +--------------+ ; Pin-Out File ; +--------------+ The pin-out file can be found in D:/altera/quartus60/indi16v/indi16.pin. +------------------------------------------------------------------+ ; Fitter Resource Usage Summary ; +---------------------------------------------+--------------------+ ; Resource ; Usage ; +---------------------------------------------+--------------------+ ; Total logic elements ; 77 / 1,270 ( 6 % ) ; ; -- Combinational with no register ; 10 ; ; -- Register only ; 58 ; ; -- Combinational with a register ; 9 ; ; ; ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 11 ; ; -- 3 input functions ; 3 ; ; -- 2 input functions ; 4 ; ; -- 1 input functions ; 28 ; ; -- 0 input functions ; 31 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 77 ; ; -- arithmetic mode ; 0 ; ; -- qfbk mode ; 1 ; ; -- register cascade mode ; 0 ; ; -- synchronous clear/load mode ; 31 ; ; -- asynchronous clear/load mode ; 8 ; ; ; ; ; Total LABs ; 11 / 127 ( 9 % ) ; ; Logic elements in carry chains ; 0 ; ; User inserted logic elements ; 0 ; ; Virtual pins ; 0 ; ; I/O pins ; 86 / 212 ( 41 % ) ; ; -- Clock pins ; 2 ; ; Global signals ; 2 ; ; UFM blocks ; 0 / 1 ( 0 % ) ; ; Global clocks ; 2 / 4 ( 50 % ) ; ; Maximum fan-out node ; CLK_I ; ; Maximum fan-out ; 67 ; ; Highest non-global fan-out signal ; Dir~514 ; ; Highest non-global fan-out ; 22 ; ; Total fan-out ; 313 ; ; Average fan-out ; 1.92 ; +---------------------------------------------+--------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Input Pins ; +-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Location assigned by ; +-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ ; ADR_I[0] ; E5 ; 1 ; 0 ; 10 ; 6 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; ADR_I[10] ; C15 ; 3 ; 17 ; 10 ; 4 ; 0 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; ADR_I[11] ; E7 ; 2 ; 6 ; 11 ; 3 ; 0 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; ADR_I[12] ; T13 ; 4 ; 14 ; 0 ; 2 ; 0 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; ADR_I[13] ; M7 ; 4 ; 5 ; 3 ; 0 ; 0 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; ADR_I[14] ; E14 ; 3 ; 17 ; 10 ; 1 ; 0 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; ADR_I[15] ; A9 ; 2 ; 9 ; 11 ; 2 ; 0 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; ADR_I[1] ; C3 ; 1 ; 0 ; 10 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; ADR_I[2] ; D2 ; 1 ; 0 ; 10 ; 5 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; ADR_I[3] ; D4 ; 2 ; 1 ; 11 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; ADR_I[4] ; D3 ; 1 ; 0 ; 10 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; ADR_I[5] ; G15 ; 3 ; 17 ; 7 ; 4 ; 0 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; ADR_I[6] ; H16 ; 3 ; 17 ; 6 ; 5 ; 0 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; ADR_I[7] ; B3 ; 2 ; 2 ; 11 ; 1 ; 0 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; ADR_I[8] ; N13 ; 3 ; 17 ; 1 ; 4 ; 0 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; ADR_I[9] ; R12 ; 4 ; 13 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; CLK_I ; H5 ; 1 ; 0 ; 7 ; 5 ; 67 ; 0 ; yes ; no ; no ; Off ; LVTTL ; Fitter ; ; CYC_I ; N15 ; 3 ; 17 ; 2 ; 4 ; 0 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; DASPN ; L14 ; 3 ; 17 ; 2 ; 3 ; 0 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; DAT_I[0] ; R4 ; 4 ; 3 ; 3 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; DAT_I[10] ; M2 ; 1 ; 0 ; 5 ; 6 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; DAT_I[11] ; R3 ; 4 ; 2 ; 3 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; DAT_I[12] ; L1 ; 1 ; 0 ; 5 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; DAT_I[13] ; P7 ; 4 ; 4 ; 3 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; DAT_I[14] ; F2 ; 1 ; 0 ; 9 ; 6 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; DAT_I[15] ; N5 ; 4 ; 2 ; 3 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; DAT_I[1] ; N6 ; 4 ; 3 ; 3 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; DAT_I[2] ; M1 ; 1 ; 0 ; 5 ; 4 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; DAT_I[3] ; L2 ; 1 ; 0 ; 5 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; DAT_I[4] ; F4 ; 1 ; 0 ; 9 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; DAT_I[5] ; E2 ; 1 ; 0 ; 9 ; 2 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; DAT_I[6] ; D1 ; 1 ; 0 ; 9 ; 0 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; DAT_I[7] ; E1 ; 1 ; 0 ; 9 ; 4 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; DAT_I[8] ; P5 ; 4 ; 2 ; 3 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; DAT_I[9] ; R5 ; 4 ; 4 ; 3 ; 1 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; DMARQ ; K16 ; 3 ; 17 ; 4 ; 1 ; 0 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; HLT_I ; H2 ; 1 ; 0 ; 7 ; 0 ; 2 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; INTRQ ; J16 ; 3 ; 17 ; 5 ; 3 ; 0 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; IORDY ; P6 ; 4 ; 3 ; 3 ; 2 ; 2 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; RST_I ; J5 ; 1 ; 0 ; 7 ; 6 ; 10 ; 0 ; yes ; no ; no ; Off ; LVTTL ; Fitter ; ; SEL_I ; A12 ; 2 ; 12 ; 11 ; 0 ; 0 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; STB_I ; G6 ; 1 ; 0 ; 7 ; 1 ; 3 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; ; WE_I ; H3 ; 1 ; 0 ; 7 ; 3 ; 1 ; 0 ; no ; no ; no ; Off ; LVTTL ; Fitter ; +-----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------+--------------+--------------+----------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Output Pins ; +-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; +-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+ ; ACK_O ; H1 ; 1 ; 0 ; 7 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; CSEL ; L15 ; 3 ; 17 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; CSN[0] ; B1 ; 2 ; 1 ; 11 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; CSN[1] ; D5 ; 2 ; 1 ; 11 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; DAT_O[0] ; G5 ; 1 ; 0 ; 8 ; 6 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; DAT_O[10] ; G1 ; 1 ; 0 ; 8 ; 5 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; DAT_O[11] ; C4 ; 2 ; 3 ; 11 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; DAT_O[12] ; L3 ; 1 ; 0 ; 4 ; 4 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; DAT_O[13] ; N3 ; 1 ; 1 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; DAT_O[14] ; P4 ; 4 ; 1 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; DAT_O[15] ; K1 ; 1 ; 0 ; 6 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; DAT_O[1] ; T2 ; 4 ; 2 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; DAT_O[2] ; G2 ; 1 ; 0 ; 8 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; DAT_O[3] ; R1 ; 4 ; 1 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; DAT_O[4] ; F6 ; 1 ; 0 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; DAT_O[5] ; D6 ; 2 ; 3 ; 11 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; DAT_O[6] ; F3 ; 1 ; 0 ; 9 ; 1 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; DAT_O[7] ; N2 ; 1 ; 0 ; 4 ; 5 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; DAT_O[8] ; P2 ; 1 ; 1 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; DAT_O[9] ; M4 ; 1 ; 0 ; 4 ; 6 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; DA[0] ; A2 ; 2 ; 2 ; 11 ; 3 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; DA[1] ; E4 ; 1 ; 0 ; 10 ; 4 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; DA[2] ; E3 ; 1 ; 0 ; 10 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; DIORN ; C6 ; 2 ; 2 ; 11 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; DIOWN ; J1 ; 1 ; 0 ; 7 ; 4 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; DMACKN ; M14 ; 3 ; 17 ; 1 ; 2 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; RESETN ; B13 ; 2 ; 14 ; 11 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; +-----------+-------+----------+--------------+--------------+-------------+-----------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Bidir Pins ; +--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+ ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Output Register ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Fast Output Connection ; Location assigned by ; Load ; +--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+ ; DD[0] ; J2 ; 1 ; 0 ; 6 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; DD[10] ; H4 ; 1 ; 0 ; 6 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; DD[11] ; K3 ; 1 ; 0 ; 5 ; 5 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; DD[12] ; L5 ; 1 ; 0 ; 4 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; DD[13] ; M3 ; 1 ; 0 ; 4 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; DD[14] ; J4 ; 1 ; 0 ; 6 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; DD[15] ; K6 ; 1 ; 0 ; 6 ; 6 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; DD[1] ; K5 ; 1 ; 0 ; 5 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; DD[2] ; G3 ; 1 ; 0 ; 8 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; DD[3] ; N1 ; 1 ; 0 ; 4 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; ; DD[4] ; G4 ; 1 ; 0 ; 8 ; 4 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; DD[5] ; K2 ; 1 ; 0 ; 6 ; 5 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; DD[6] ; F1 ; 1 ; 0 ; 8 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; DD[7] ; J3 ; 1 ; 0 ; 6 ; 4 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; DD[8] ; K4 ; 1 ; 0 ; 5 ; 3 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; yes ; Fitter ; 10 pF ; ; DD[9] ; L4 ; 1 ; 0 ; 4 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; no ; Off ; LVTTL ; 16mA ; no ; Fitter ; 10 pF ; +--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+-----------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+------------------------+----------------------+-------+ +------------------------------------------------------------+ ; I/O Bank Usage ; +----------+------------------+---------------+--------------+ ; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; +----------+------------------+---------------+--------------+ ; 1 ; 49 / 51 ( 96 % ) ; 3.3V ; -- ; ; 2 ; 12 / 53 ( 23 % ) ; 3.3V ; -- ; ; 3 ; 11 / 55 ( 20 % ) ; 3.3V ; -- ; ; 4 ; 14 / 53 ( 26 % ) ; 3.3V ; -- ; +----------+------------------+---------------+--------------+ +----------------------------------------------------------------------------------------------------------------------------------------------+ ; All Package Pins ; +----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+ ; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; +----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+ ; A1 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; A2 ; 212 ; 2 ; DA[0] ; output ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; A3 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; A4 ; 204 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; A5 ; 200 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; A6 ; 196 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; A7 ; 192 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; A8 ; 189 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; A9 ; 188 ; 2 ; ADR_I[15] ; input ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; A10 ; 184 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; A11 ; 180 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; A12 ; 176 ; 2 ; SEL_I ; input ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; A13 ; 172 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; A14 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; A15 ; 166 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; A16 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; B1 ; 214 ; 2 ; CSN[0] ; output ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; B2 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; B3 ; 210 ; 2 ; ADR_I[7] ; input ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; B4 ; 206 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; B5 ; 202 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; B6 ; 198 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; B7 ; 194 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; B8 ; 190 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; B9 ; 186 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; B10 ; 182 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; B11 ; 178 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; B12 ; 174 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; B13 ; 170 ; 2 ; RESETN ; output ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; B14 ; 168 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; B15 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; B16 ; 164 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; C1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; C2 ; 1 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; C3 ; 3 ; 1 ; ADR_I[1] ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; C4 ; 208 ; 2 ; DAT_O[11] ; output ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; C5 ; 211 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; C6 ; 209 ; 2 ; DIORN ; output ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; C7 ; 203 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; C8 ; 195 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; C9 ; 183 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; C10 ; 175 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; C11 ; 169 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; C12 ; 165 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; C13 ; 163 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; C14 ; 160 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; C15 ; 158 ; 3 ; ADR_I[10] ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; C16 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; D1 ; 7 ; 1 ; DAT_I[6] ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; D2 ; 5 ; 1 ; ADR_I[2] ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; D3 ; 0 ; 1 ; ADR_I[4] ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; D4 ; 215 ; 2 ; ADR_I[3] ; input ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; D5 ; 213 ; 2 ; CSN[1] ; output ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; D6 ; 207 ; 2 ; DAT_O[5] ; output ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; D7 ; 201 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; D8 ; 193 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; D9 ; 185 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; D10 ; 177 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; D11 ; 171 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; D12 ; 167 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; D13 ; 162 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; D14 ; 156 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; D15 ; 154 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; D16 ; 152 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; E1 ; 11 ; 1 ; DAT_I[7] ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; E2 ; 9 ; 1 ; DAT_I[5] ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; E3 ; 2 ; 1 ; DA[2] ; output ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; E4 ; 4 ; 1 ; DA[1] ; output ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; E5 ; 6 ; 1 ; ADR_I[0] ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; E6 ; 205 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; E7 ; 199 ; 2 ; ADR_I[11] ; input ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; E8 ; 191 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; E9 ; 187 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; E10 ; 179 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; E11 ; 173 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; E12 ; 157 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; E13 ; 159 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; E14 ; 161 ; 3 ; ADR_I[14] ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; E15 ; 150 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; E16 ; 148 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; F1 ; 15 ; 1 ; DD[6] ; bidir ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; F2 ; 13 ; 1 ; DAT_I[14] ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; F3 ; 8 ; 1 ; DAT_O[6] ; output ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; F4 ; 10 ; 1 ; DAT_I[4] ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; F5 ; 12 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; F6 ; 14 ; 1 ; DAT_O[4] ; output ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; F7 ; 197 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; F8 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; F9 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; F10 ; 181 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; F11 ; 149 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; F12 ; 151 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; F13 ; 153 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; F14 ; 155 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; F15 ; 146 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; F16 ; 144 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; G1 ; 19 ; 1 ; DAT_O[10] ; output ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; G2 ; 17 ; 1 ; DAT_O[2] ; output ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; G3 ; 16 ; 1 ; DD[2] ; bidir ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; G4 ; 18 ; 1 ; DD[4] ; bidir ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; G5 ; 20 ; 1 ; DAT_O[0] ; output ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; G6 ; 22 ; 1 ; STB_I ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; G7 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; G8 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; G9 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; G10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; G11 ; 143 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; G12 ; 141 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; G13 ; 145 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; G14 ; 147 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; G15 ; 142 ; 3 ; ADR_I[5] ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; G16 ; 140 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; H1 ; 23 ; 1 ; ACK_O ; output ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; H2 ; 21 ; 1 ; HLT_I ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; H3 ; 24 ; 1 ; WE_I ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; H4 ; 28 ; 1 ; DD[10] ; bidir ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; H5 ; 26 ; 1 ; CLK_I ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; H6 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; H7 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; ; H8 ; ; ; VCCINT ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; H9 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; ; H10 ; ; ; VCCINT ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; H11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; H12 ; 135 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; H13 ; 137 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; H14 ; 139 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; H15 ; 138 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; H16 ; 136 ; 3 ; ADR_I[6] ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; J1 ; 25 ; 1 ; DIOWN ; output ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; J2 ; 29 ; 1 ; DD[0] ; bidir ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; J3 ; 32 ; 1 ; DD[7] ; bidir ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; J4 ; 30 ; 1 ; DD[14] ; bidir ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; J5 ; 27 ; 1 ; RST_I ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; J6 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; J7 ; ; ; VCCINT ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; J8 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; ; J9 ; ; ; VCCINT ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; J10 ; ; ; GNDINT ; gnd ; ; ; -- ; ; -- ; -- ; ; J11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; J12 ; 134 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; J13 ; 133 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; J14 ; 131 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; J15 ; 130 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; J16 ; 132 ; 3 ; INTRQ ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; K1 ; 31 ; 1 ; DAT_O[15] ; output ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; K2 ; 33 ; 1 ; DD[5] ; bidir ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; K3 ; 40 ; 1 ; DD[11] ; bidir ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; K4 ; 38 ; 1 ; DD[8] ; bidir ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; K5 ; 36 ; 1 ; DD[1] ; bidir ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; K6 ; 34 ; 1 ; DD[15] ; bidir ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; K7 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; K8 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; K9 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; K10 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; K11 ; 129 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; K12 ; 127 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; K13 ; 125 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; K14 ; 123 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; K15 ; 126 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; K16 ; 128 ; 3 ; DMARQ ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; L1 ; 35 ; 1 ; DAT_I[12] ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; L2 ; 37 ; 1 ; DAT_I[3] ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; L3 ; 46 ; 1 ; DAT_O[12] ; output ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; L4 ; 44 ; 1 ; DD[9] ; bidir ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; L5 ; 42 ; 1 ; DD[12] ; bidir ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; L6 ; 51 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; ; L7 ; 73 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; L8 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; L9 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; L10 ; 87 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; L11 ; 121 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; L12 ; 119 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; L13 ; 117 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; L14 ; 115 ; 3 ; DASPN ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; L15 ; 122 ; 3 ; CSEL ; output ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; L16 ; 124 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; M1 ; 39 ; 1 ; DAT_I[2] ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; M2 ; 41 ; 1 ; DAT_I[10] ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; M3 ; 43 ; 1 ; DD[13] ; bidir ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; M4 ; 48 ; 1 ; DAT_O[9] ; output ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; M5 ; 53 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; ; M6 ; 65 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; M7 ; 71 ; 4 ; ADR_I[13] ; input ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; M8 ; 85 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; M9 ; 86 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; M10 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; M11 ; 95 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; M12 ; 101 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; M13 ; 113 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; M14 ; 111 ; 3 ; DMACKN ; output ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; M15 ; 118 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; M16 ; 120 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; N1 ; 45 ; 1 ; DD[3] ; bidir ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; N2 ; 47 ; 1 ; DAT_O[7] ; output ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; N3 ; 49 ; 1 ; DAT_O[13] ; output ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; N4 ; 50 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; ; N5 ; 59 ; 4 ; DAT_I[15] ; input ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; N6 ; 63 ; 4 ; DAT_I[1] ; input ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; N7 ; 69 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; N8 ; 77 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; N9 ; 79 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; N10 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; N11 ; 97 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; N12 ; 103 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; N13 ; 109 ; 3 ; ADR_I[8] ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; N14 ; 112 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; N15 ; 114 ; 3 ; CYC_I ; input ; LVTTL ; ; Row I/O ; N ; no ; Off ; ; N16 ; 116 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; P1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; P2 ; 54 ; 1 ; DAT_O[8] ; output ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; P3 ; 52 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; ; P4 ; 55 ; 4 ; DAT_O[14] ; output ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; P5 ; 57 ; 4 ; DAT_I[8] ; input ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; P6 ; 61 ; 4 ; IORDY ; input ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; P7 ; 67 ; 4 ; DAT_I[13] ; input ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; P8 ; 75 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; P9 ; 83 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; P10 ; 93 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; P11 ; 99 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; P12 ; 105 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; P13 ; 107 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; P14 ; 108 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; P15 ; 110 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ; ; P16 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; R1 ; 56 ; 4 ; DAT_O[3] ; output ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; R2 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; R3 ; 60 ; 4 ; DAT_I[11] ; input ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; R4 ; 62 ; 4 ; DAT_I[0] ; input ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; R5 ; 66 ; 4 ; DAT_I[9] ; input ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; R6 ; 70 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; R7 ; 74 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; R8 ; 78 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; R9 ; 82 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; R10 ; 88 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; R11 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; R12 ; 96 ; 4 ; ADR_I[9] ; input ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; R13 ; 100 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; R14 ; 102 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; R15 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; R16 ; 106 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; T1 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; ; T2 ; 58 ; 4 ; DAT_O[1] ; output ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; T3 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; T4 ; 64 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; T5 ; 68 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; T6 ; 72 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; T7 ; 76 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; T8 ; 80 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; T9 ; 81 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; T10 ; 84 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; T11 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; T12 ; 94 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; T13 ; 98 ; 4 ; ADR_I[12] ; input ; LVTTL ; ; Column I/O ; N ; no ; Off ; ; T14 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; ; T15 ; 104 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ; ; T16 ; ; ; GNDIO ; gnd ; ; ; -- ; ; -- ; -- ; +----------+------------+----------+----------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +-------------------------------------------------------------+ ; Output Pin Default Load For Reported TCO ; +----------------------------+-------+------------------------+ ; I/O Standard ; Load ; Termination Resistance ; +----------------------------+-------+------------------------+ ; LVTTL ; 10 pF ; Not Available ; ; LVCMOS ; 10 pF ; Not Available ; ; 2.5 V ; 10 pF ; Not Available ; ; 1.8 V ; 10 pF ; Not Available ; ; 1.5 V ; 10 pF ; Not Available ; ; 3.3V Schmitt Trigger Input ; 10 pF ; Not Available ; ; 2.5V Schmitt Trigger Input ; 10 pF ; Not Available ; ; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; +----------------------------+-------+------------------------+ Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fitter Resource Utilization by Entity ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+ ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+ ; |ata ; 77 (77) ; 67 ; 0 ; 86 ; 0 ; 10 (10) ; 58 (58) ; 9 (9) ; 0 (0) ; 1 (1) ; |ata ; +----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +--------------------------------------+ ; Delay Chain Summary ; +-----------+----------+---------------+ ; Name ; Pin Type ; Pad to Core 0 ; +-----------+----------+---------------+ ; ADR_I[5] ; Input ; 0 ; ; ADR_I[6] ; Input ; 0 ; ; ADR_I[7] ; Input ; 0 ; ; ADR_I[8] ; Input ; 0 ; ; ADR_I[9] ; Input ; 0 ; ; ADR_I[10] ; Input ; 0 ; ; ADR_I[11] ; Input ; 0 ; ; ADR_I[12] ; Input ; 0 ; ; ADR_I[13] ; Input ; 0 ; ; ADR_I[14] ; Input ; 0 ; ; ADR_I[15] ; Input ; 0 ; ; SEL_I ; Input ; 0 ; ; CYC_I ; Input ; 0 ; ; DMARQ ; Input ; 0 ; ; INTRQ ; Input ; 0 ; ; DASPN ; Input ; 0 ; ; STB_I ; Input ; 0 ; ; CLK_I ; Input ; 0 ; ; RST_I ; Input ; 0 ; ; HLT_I ; Input ; 0 ; ; IORDY ; Input ; 0 ; ; WE_I ; Input ; 1 ; ; ADR_I[0] ; Input ; 1 ; ; ADR_I[1] ; Input ; 1 ; ; ADR_I[2] ; Input ; 1 ; ; ADR_I[3] ; Input ; 0 ; ; ADR_I[4] ; Input ; 1 ; ; DAT_I[0] ; Input ; 0 ; ; DAT_I[1] ; Input ; 0 ; ; DAT_I[2] ; Input ; 1 ; ; DAT_I[3] ; Input ; 1 ; ; DAT_I[4] ; Input ; 1 ; ; DAT_I[5] ; Input ; 1 ; ; DAT_I[6] ; Input ; 1 ; ; DAT_I[7] ; Input ; 1 ; ; DAT_I[8] ; Input ; 1 ; ; DAT_I[9] ; Input ; 0 ; ; DAT_I[10] ; Input ; 1 ; ; DAT_I[11] ; Input ; 1 ; ; DAT_I[12] ; Input ; 1 ; ; DAT_I[13] ; Input ; 0 ; ; DAT_I[14] ; Input ; 1 ; ; DAT_I[15] ; Input ; 0 ; ; DAT_O[0] ; Output ; -- ; ; DAT_O[1] ; Output ; -- ; ; DAT_O[2] ; Output ; -- ; ; DAT_O[3] ; Output ; -- ; ; DAT_O[4] ; Output ; -- ; ; DAT_O[5] ; Output ; -- ; ; DAT_O[6] ; Output ; -- ; ; DAT_O[7] ; Output ; -- ; ; DAT_O[8] ; Output ; -- ; ; DAT_O[9] ; Output ; -- ; ; DAT_O[10] ; Output ; -- ; ; DAT_O[11] ; Output ; -- ; ; DAT_O[12] ; Output ; -- ; ; DAT_O[13] ; Output ; -- ; ; DAT_O[14] ; Output ; -- ; ; DAT_O[15] ; Output ; -- ; ; ACK_O ; Output ; -- ; ; RESETN ; Output ; -- ; ; DIOWN ; Output ; -- ; ; DIORN ; Output ; -- ; ; CSEL ; Output ; -- ; ; DMACKN ; Output ; -- ; ; DA[0] ; Output ; -- ; ; DA[1] ; Output ; -- ; ; DA[2] ; Output ; -- ; ; CSN[0] ; Output ; -- ; ; CSN[1] ; Output ; -- ; ; DD[0] ; Bidir ; 0 ; ; DD[1] ; Bidir ; 1 ; ; DD[2] ; Bidir ; 1 ; ; DD[3] ; Bidir ; 1 ; ; DD[4] ; Bidir ; 1 ; ; DD[5] ; Bidir ; 0 ; ; DD[6] ; Bidir ; 1 ; ; DD[7] ; Bidir ; 0 ; ; DD[8] ; Bidir ; 0 ; ; DD[9] ; Bidir ; 1 ; ; DD[10] ; Bidir ; 0 ; ; DD[11] ; Bidir ; 0 ; ; DD[12] ; Bidir ; 1 ; ; DD[13] ; Bidir ; 1 ; ; DD[14] ; Bidir ; 1 ; ; DD[15] ; Bidir ; 0 ; +-----------+----------+---------------+ +---------------------------------------------------------------------------------------------------------+ ; Control Signals ; +-------------+--------------+---------+---------------+--------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; +-------------+--------------+---------+---------------+--------+----------------------+------------------+ ; Busy ; LC_X1_Y7_N8 ; 11 ; Clock enable ; no ; -- ; -- ; ; CLK_I ; PIN_H5 ; 67 ; Clock ; yes ; Global clock ; GCLK0 ; ; DA[0]~45 ; LC_X1_Y10_N1 ; 5 ; Clock enable ; no ; -- ; -- ; ; DD[0]~en ; LC_X1_Y6_N0 ; 16 ; Output enable ; no ; -- ; -- ; ; Dir~514 ; LC_X1_Y7_N0 ; 22 ; Clock enable ; no ; -- ; -- ; ; RST_I ; PIN_J5 ; 10 ; Async. clear ; yes ; Global clock ; GCLK1 ; ; Read[0]~130 ; LC_X1_Y7_N3 ; 16 ; Clock enable ; no ; -- ; -- ; ; comb~34 ; LC_X1_Y7_N6 ; 17 ; Clock enable ; no ; -- ; -- ; +-------------+--------------+---------+---------------+--------+----------------------+------------------+ +----------------------------------------------------------------------+ ; Global & Other Fast Signals ; +-------+----------+---------+----------------------+------------------+ ; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; +-------+----------+---------+----------------------+------------------+ ; CLK_I ; PIN_H5 ; 67 ; Global clock ; GCLK0 ; ; RST_I ; PIN_J5 ; 10 ; Global clock ; GCLK1 ; +-------+----------+---------+----------------------+------------------+ +---------------------------------+ ; Non-Global High Fan-Out Signals ; +-------------+-------------------+ ; Name ; Fan-Out ; +-------------+-------------------+ ; Dir~514 ; 22 ; ; comb~34 ; 17 ; ; DD[0]~en ; 16 ; ; Read[0]~130 ; 16 ; ; Busy ; 11 ; ; Seq[2] ; 9 ; ; Seq[1] ; 9 ; ; Seq[0] ; 8 ; ; DA[0]~45 ; 5 ; ; STB_I ; 3 ; ; Dir ; 3 ; ; IORDY ; 2 ; ; HLT_I ; 2 ; ; Mux8~35 ; 2 ; ; DIOWN~162 ; 2 ; ; DIOWN~161 ; 2 ; ; Read[0]~129 ; 2 ; ; DIORN~reg0 ; 2 ; ; DIOWN~reg0 ; 2 ; ; DD[15]~0 ; 1 ; ; DD[14]~1 ; 1 ; ; DD[13]~2 ; 1 ; ; DD[12]~3 ; 1 ; ; DD[11]~4 ; 1 ; ; DD[10]~5 ; 1 ; ; DD[9]~6 ; 1 ; ; DD[8]~7 ; 1 ; ; DD[7]~8 ; 1 ; ; DD[6]~9 ; 1 ; ; DD[5]~10 ; 1 ; ; DD[4]~11 ; 1 ; ; DD[3]~12 ; 1 ; ; DD[2]~13 ; 1 ; ; DD[1]~14 ; 1 ; ; DD[0]~15 ; 1 ; ; DAT_I[15] ; 1 ; ; DAT_I[14] ; 1 ; ; DAT_I[13] ; 1 ; ; DAT_I[12] ; 1 ; ; DAT_I[11] ; 1 ; ; DAT_I[10] ; 1 ; ; DAT_I[9] ; 1 ; ; DAT_I[8] ; 1 ; ; DAT_I[7] ; 1 ; ; DAT_I[6] ; 1 ; ; DAT_I[5] ; 1 ; ; DAT_I[4] ; 1 ; ; DAT_I[3] ; 1 ; ; DAT_I[2] ; 1 ; ; DAT_I[1] ; 1 ; +-------------+-------------------+ +---------------------------------------------------+ ; Interconnect Usage Summary ; +----------------------------+----------------------+ ; Interconnect Resource Type ; Usage ; +----------------------------+----------------------+ ; C4s ; 76 / 2,870 ( 3 % ) ; ; Direct links ; 13 / 3,938 ( < 1 % ) ; ; Global clocks ; 2 / 4 ( 50 % ) ; ; LAB clocks ; 7 / 72 ( 10 % ) ; ; LUT chains ; 2 / 1,143 ( < 1 % ) ; ; Local interconnects ; 112 / 3,938 ( 3 % ) ; ; R4s ; 37 / 2,832 ( 1 % ) ; +----------------------------+----------------------+ +---------------------------------------------------------------------------+ ; LAB Logic Elements ; +--------------------------------------------+------------------------------+ ; Number of Logic Elements (Average = 7.00) ; Number of LABs (Total = 11) ; +--------------------------------------------+------------------------------+ ; 1 ; 1 ; ; 2 ; 1 ; ; 3 ; 0 ; ; 4 ; 0 ; ; 5 ; 0 ; ; 6 ; 1 ; ; 7 ; 2 ; ; 8 ; 1 ; ; 9 ; 4 ; ; 10 ; 1 ; +--------------------------------------------+------------------------------+ +-------------------------------------------------------------------+ ; LAB-wide Signals ; +------------------------------------+------------------------------+ ; LAB-wide Signals (Average = 2.18) ; Number of LABs (Total = 11) ; +------------------------------------+------------------------------+ ; 1 Async. clear ; 4 ; ; 1 Clock ; 11 ; ; 1 Clock enable ; 6 ; ; 2 Clock enables ; 3 ; +------------------------------------+------------------------------+ +----------------------------------------------------------------------------+ ; LAB Signals Sourced ; +---------------------------------------------+------------------------------+ ; Number of Signals Sourced (Average = 7.18) ; Number of LABs (Total = 11) ; +---------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 1 ; ; 2 ; 1 ; ; 3 ; 0 ; ; 4 ; 0 ; ; 5 ; 0 ; ; 6 ; 1 ; ; 7 ; 1 ; ; 8 ; 1 ; ; 9 ; 5 ; ; 10 ; 1 ; +---------------------------------------------+------------------------------+ +--------------------------------------------------------------------------------+ ; LAB Signals Sourced Out ; +-------------------------------------------------+------------------------------+ ; Number of Signals Sourced Out (Average = 6.09) ; Number of LABs (Total = 11) ; +-------------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 1 ; ; 2 ; 1 ; ; 3 ; 0 ; ; 4 ; 0 ; ; 5 ; 2 ; ; 6 ; 1 ; ; 7 ; 3 ; ; 8 ; 0 ; ; 9 ; 3 ; +-------------------------------------------------+------------------------------+ +----------------------------------------------------------------------------+ ; LAB Distinct Inputs ; +---------------------------------------------+------------------------------+ ; Number of Distinct Inputs (Average = 8.64) ; Number of LABs (Total = 11) ; +---------------------------------------------+------------------------------+ ; 0 ; 0 ; ; 1 ; 0 ; ; 2 ; 1 ; ; 3 ; 0 ; ; 4 ; 1 ; ; 5 ; 1 ; ; 6 ; 0 ; ; 7 ; 0 ; ; 8 ; 1 ; ; 9 ; 2 ; ; 10 ; 1 ; ; 11 ; 1 ; ; 12 ; 2 ; ; 13 ; 1 ; +---------------------------------------------+------------------------------+ +--------------------------------------------------------------------+ ; Fitter Device Options ; +----------------------------------------------+---------------------+ ; Option ; Setting ; +----------------------------------------------+---------------------+ ; Enable user-supplied start-up clock (CLKUSR) ; Off ; ; Enable device-wide reset (DEV_CLRn) ; Off ; ; Enable device-wide output enable (DEV_OE) ; Off ; ; Enable INIT_DONE output ; Off ; ; Configuration scheme ; Passive Serial ; ; Reserve all unused pins ; As input tri-stated ; ; Base pin-out file on sameframe device ; Off ; +----------------------------------------------+---------------------+ +----------------------------+ ; Advanced Data - General ; +--------------------+-------+ ; Name ; Value ; +--------------------+-------+ ; Desired User Slack ; 0 ; ; Fit Attempts ; 1 ; +--------------------+-------+ +----------------------------------------------------------------------------------------------+ ; Advanced Data - Placement Preparation ; +--------------------------------------------------------------------------------+-------------+ ; Name ; Value ; +--------------------------------------------------------------------------------+-------------+ ; Mid Wire Use - Fit Attempt 1 ; 6 ; ; Mid Slack - Fit Attempt 1 ; -9625 ; ; Internal Atom Count - Fit Attempt 1 ; 77 ; ; LE/ALM Count - Fit Attempt 1 ; 77 ; ; LAB Count - Fit Attempt 1 ; 11 ; ; Outputs per Lab - Fit Attempt 1 ; 4.727 ; ; Inputs per LAB - Fit Attempt 1 ; 5.818 ; ; Global Inputs per LAB - Fit Attempt 1 ; 1.364 ; ; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1 ; 0:11 ; ; LAB Constraint 'ce + sync load' - Fit Attempt 1 ; 0:1;1:5;2:5 ; ; LAB Constraint 'non-global controls' - Fit Attempt 1 ; 0:1;1:5;2:5 ; ; LAB Constraint 'un-route combination' - Fit Attempt 1 ; 0:1;1:5;2:5 ; ; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1 ; 1:4;2:6;3:1 ; ; LAB Constraint 'un-route with async_clear' - Fit Attempt 1 ; 1:4;2:6;3:1 ; ; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1 ; 0:11 ; ; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1 ; 0:11 ; ; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1 ; 0:1;1:10 ; ; LAB Constraint 'global control signals' - Fit Attempt 1 ; 1:7;2:4 ; ; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1 ; 1:4;2:7 ; ; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1 ; 0:11 ; ; LAB Constraint 'aload_aclr pair' - Fit Attempt 1 ; 1:9;2:2 ; ; LAB Constraint 'sload_sclear pair' - Fit Attempt 1 ; 0:10;1:1 ; ; LAB Constraint 'invert_a constraint' - Fit Attempt 1 ; 0:9;1:2 ; ; LAB Constraint 'has placement constraint' - Fit Attempt 1 ; 0:11 ; ; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:11 ; ; LEs in Chains - Fit Attempt 1 ; 0 ; ; LEs in Long Chains - Fit Attempt 1 ; 0 ; ; LABs with Chains - Fit Attempt 1 ; 0 ; ; LABs with Multiple Chains - Fit Attempt 1 ; 0 ; ; Time - Fit Attempt 1 ; 0 ; ; Time in tsm_tan.dll - Fit Attempt 1 ; 0.031 ; +--------------------------------------------------------------------------------+-------------+ +---------------------------------------------+ ; Advanced Data - Placement ; +-------------------------------------+-------+ ; Name ; Value ; +-------------------------------------+-------+ ; Early Wire Use - Fit Attempt 1 ; 1 ; ; Early Slack - Fit Attempt 1 ; -9154 ; ; Mid Wire Use - Fit Attempt 1 ; 3 ; ; Mid Slack - Fit Attempt 1 ; -8593 ; ; Late Wire Use - Fit Attempt 1 ; 3 ; ; Late Slack - Fit Attempt 1 ; -7993 ; ; Time - Fit Attempt 1 ; 3 ; ; Time in tsm_tan.dll - Fit Attempt 1 ; 0.435 ; +-------------------------------------+-------+ +---------------------------------------------+ ; Advanced Data - Routing ; +-------------------------------------+-------+ ; Name ; Value ; +-------------------------------------+-------+ ; Early Slack - Fit Attempt 1 ; -8134 ; ; Early Wire Use - Fit Attempt 1 ; 2 ; ; Peak Regional Wire - Fit Attempt 1 ; 5 ; ; Mid Slack - Fit Attempt 1 ; -8134 ; ; Late Slack - Fit Attempt 1 ; -8134 ; ; Late Slack - Fit Attempt 1 ; -8134 ; ; Late Wire Use - Fit Attempt 1 ; 3 ; ; Time - Fit Attempt 1 ; 1 ; ; Time in tsm_tan.dll - Fit Attempt 1 ; 0.219 ; +-------------------------------------+-------+ +-----------------+ ; Fitter Messages ; +-----------------+ Info: ******************************************************************* Info: Running Quartus II Fitter Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Web Edition Info: Processing started: Wed Aug 22 00:01:05 2007 Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off indi16 -c indi16 Info: Selected device EPM1270F256C5 for design "indi16" Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices Info: Device EPM570F256C5 is compatible Info: Device EPM570F256I5 is compatible Info: Device EPM1270F256I5 is compatible Info: Device EPM2210F256C5 is compatible Info: Device EPM2210F256I5 is compatible Info: No exact pin location assignment(s) for 86 pins of 86 total pins Info: Pin ADR_I[5] not assigned to an exact location on the device Info: Pin ADR_I[6] not assigned to an exact location on the device Info: Pin ADR_I[7] not assigned to an exact location on the device Info: Pin ADR_I[8] not assigned to an exact location on the device Info: Pin ADR_I[9] not assigned to an exact location on the device Info: Pin ADR_I[10] not assigned to an exact location on the device Info: Pin ADR_I[11] not assigned to an exact location on the device Info: Pin ADR_I[12] not assigned to an exact location on the device Info: Pin ADR_I[13] not assigned to an exact location on the device Info: Pin ADR_I[14] not assigned to an exact location on the device Info: Pin ADR_I[15] not assigned to an exact location on the device Info: Pin DAT_O[0] not assigned to an exact location on the device Info: Pin DAT_O[1] not assigned to an exact location on the device Info: Pin DAT_O[2] not assigned to an exact location on the device Info: Pin DAT_O[3] not assigned to an exact location on the device Info: Pin DAT_O[4] not assigned to an exact location on the device Info: Pin DAT_O[5] not assigned to an exact location on the device Info: Pin DAT_O[6] not assigned to an exact location on the device Info: Pin DAT_O[7] not assigned to an exact location on the device Info: Pin DAT_O[8] not assigned to an exact location on the device Info: Pin DAT_O[9] not assigned to an exact location on the device Info: Pin DAT_O[10] not assigned to an exact location on the device Info: Pin DAT_O[11] not assigned to an exact location on the device Info: Pin DAT_O[12] not assigned to an exact location on the device Info: Pin DAT_O[13] not assigned to an exact location on the device Info: Pin DAT_O[14] not assigned to an exact location on the device Info: Pin DAT_O[15] not assigned to an exact location on the device Info: Pin SEL_I not assigned to an exact location on the device Info: Pin ACK_O not assigned to an exact location on the device Info: Pin CYC_I not assigned to an exact location on the device Info: Pin RESETN not assigned to an exact location on the device Info: Pin DMARQ not assigned to an exact location on the device Info: Pin DIOWN not assigned to an exact location on the device Info: Pin DIORN not assigned to an exact location on the device Info: Pin CSEL not assigned to an exact location on the device Info: Pin DMACKN not assigned to an exact location on the device Info: Pin INTRQ not assigned to an exact location on the device Info: Pin DA[0] not assigned to an exact location on the device Info: Pin DA[1] not assigned to an exact location on the device Info: Pin DA[2] not assigned to an exact location on the device Info: Pin CSN[0] not assigned to an exact location on the device Info: Pin CSN[1] not assigned to an exact location on the device Info: Pin DASPN not assigned to an exact location on the device Info: Pin DD[0] not assigned to an exact location on the device Info: Pin DD[1] not assigned to an exact location on the device Info: Pin DD[2] not assigned to an exact location on the device Info: Pin DD[3] not assigned to an exact location on the device Info: Pin DD[4] not assigned to an exact location on the device Info: Pin DD[5] not assigned to an exact location on the device Info: Pin DD[6] not assigned to an exact location on the device Info: Pin DD[7] not assigned to an exact location on the device Info: Pin DD[8] not assigned to an exact location on the device Info: Pin DD[9] not assigned to an exact location on the device Info: Pin DD[10] not assigned to an exact location on the device Info: Pin DD[11] not assigned to an exact location on the device Info: Pin DD[12] not assigned to an exact location on the device Info: Pin DD[13] not assigned to an exact location on the device Info: Pin DD[14] not assigned to an exact location on the device Info: Pin DD[15] not assigned to an exact location on the device Info: Pin STB_I not assigned to an exact location on the device Info: Pin CLK_I not assigned to an exact location on the device Info: Pin RST_I not assigned to an exact location on the device Info: Pin HLT_I not assigned to an exact location on the device Info: Pin IORDY not assigned to an exact location on the device Info: Pin WE_I not assigned to an exact location on the device Info: Pin ADR_I[0] not assigned to an exact location on the device Info: Pin ADR_I[1] not assigned to an exact location on the device Info: Pin ADR_I[2] not assigned to an exact location on the device Info: Pin ADR_I[3] not assigned to an exact location on the device Info: Pin ADR_I[4] not assigned to an exact location on the device Info: Pin DAT_I[0] not assigned to an exact location on the device Info: Pin DAT_I[1] not assigned to an exact location on the device Info: Pin DAT_I[2] not assigned to an exact location on the device Info: Pin DAT_I[3] not assigned to an exact location on the device Info: Pin DAT_I[4] not assigned to an exact location on the device Info: Pin DAT_I[5] not assigned to an exact location on the device Info: Pin DAT_I[6] not assigned to an exact location on the device Info: Pin DAT_I[7] not assigned to an exact location on the device Info: Pin DAT_I[8] not assigned to an exact location on the device Info: Pin DAT_I[9] not assigned to an exact location on the device Info: Pin DAT_I[10] not assigned to an exact location on the device Info: Pin DAT_I[11] not assigned to an exact location on the device Info: Pin DAT_I[12] not assigned to an exact location on the device Info: Pin DAT_I[13] not assigned to an exact location on the device Info: Pin DAT_I[14] not assigned to an exact location on the device Info: Pin DAT_I[15] not assigned to an exact location on the device Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements Info: Assuming a global fmax requirement of 1000 MHz Info: Assuming a global tsu requirement of 2.0 ns Info: Assuming a global tco requirement of 1.0 ns Info: Assuming a global tpd requirement of 1.0 ns Extra Info: Performing register packing on registers with non-logic cell location assignments Extra Info: Completed register packing on registers with non-logic cell location assignments Info: Completed User Assigned Global Signals Promotion Operation Info: Automatically promoted signal "CLK_I" to use Global clock in PIN H5 Info: Automatically promoted some destinations of signal "RST_I" to use Global clock in PIN J5 Info: Destination "Read[0]~129" may be non-global or may not use global clock Info: Destination "Dir~514" may be non-global or may not use global clock Info: Completed Auto Global Promotion Operation Info: Starting register packing Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option Extra Info: Moving registers into LUTs to improve timing and density Info: Started processing fast register assignments Info: Finished processing fast register assignments Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00 Info: Finished register packing: elapsed time is 00:00:00 Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement Info: Number of I/O pins in group: 84 (unused VREF, 3.30 VCCIO, 41 input, 27 output, 16 bidirectional) Info: I/O standards used: LVTTL. Info: I/O bank details before I/O pin placement Info: Statistics of I/O banks Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used -- 49 pins available Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 53 pins available Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 55 pins available Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 53 pins available Info: Starting Vectorless Power Activity Estimation Info: Completed Vectorless Power Activity Estimation Warning: Ignored locations or region assignments to the following nodes Warning: Node "ADC_CLK" is assigned to location or region, but does not exist in design Warning: Node "ADC_CS" is assigned to location or region, but does not exist in design Warning: Node "ADC_DIN" is assigned to location or region, but does not exist in design Warning: Node "ADC_DOUT" is assigned to location or region, but does not exist in design Warning: Node "ADC_SHDN" is assigned to location or region, but does not exist in design Warning: Node "ADC_SSTRB" is assigned to location or region, but does not exist in design Warning: Node "A[0]" is assigned to location or region, but does not exist in design Warning: Node "A[10]" is assigned to location or region, but does not exist in design Warning: Node "A[11]" is assigned to location or region, but does not exist in design Warning: Node "A[12]" is assigned to location or region, but does not exist in design Warning: Node "A[13]" is assigned to location or region, but does not exist in design Warning: Node "A[14]" is assigned to location or region, but does not exist in design Warning: Node "A[15]" is assigned to location or region, but does not exist in design Warning: Node "A[16]" is assigned to location or region, but does not exist in design Warning: Node "A[1]" is assigned to location or region, but does not exist in design Warning: Node "A[2]" is assigned to location or region, but does not exist in design Warning: Node "A[3]" is assigned to location or region, but does not exist in design Warning: Node "A[4]" is assigned to location or region, but does not exist in design Warning: Node "A[5]" is assigned to location or region, but does not exist in design Warning: Node "A[6]" is assigned to location or region, but does not exist in design Warning: Node "A[7]" is assigned to location or region, but does not exist in design Warning: Node "A[8]" is assigned to location or region, but does not exist in design Warning: Node "A[9]" is assigned to location or region, but does not exist in design Warning: Node "CEN" is assigned to location or region, but does not exist in design Warning: Node "CLK" is assigned to location or region, but does not exist in design Warning: Node "D[0]" is assigned to location or region, but does not exist in design Warning: Node "D[1]" is assigned to location or region, but does not exist in design Warning: Node "D[2]" is assigned to location or region, but does not exist in design Warning: Node "D[3]" is assigned to location or region, but does not exist in design Warning: Node "D[4]" is assigned to location or region, but does not exist in design Warning: Node "D[5]" is assigned to location or region, but does not exist in design Warning: Node "D[6]" is assigned to location or region, but does not exist in design Warning: Node "D[7]" is assigned to location or region, but does not exist in design Warning: Node "GSEL_INT" is assigned to location or region, but does not exist in design Warning: Node "GSEL_IO" is assigned to location or region, but does not exist in design Warning: Node "IO_V_ADC" is assigned to location or region, but does not exist in design Warning: Node "LCD_DB[0]" is assigned to location or region, but does not exist in design Warning: Node "LCD_DB[1]" is assigned to location or region, but does not exist in design Warning: Node "LCD_DB[2]" is assigned to location or region, but does not exist in design Warning: Node "LCD_DB[3]" is assigned to location or region, but does not exist in design Warning: Node "LCD_DB[4]" is assigned to location or region, but does not exist in design Warning: Node "LCD_DB[5]" is assigned to location or region, but does not exist in design Warning: Node "LCD_DB[6]" is assigned to location or region, but does not exist in design Warning: Node "LCD_DB[7]" is assigned to location or region, but does not exist in design Warning: Node "LCD_E" is assigned to location or region, but does not exist in design Warning: Node "LCD_RS" is assigned to location or region, but does not exist in design Warning: Node "LCD_RW" is assigned to location or region, but does not exist in design Warning: Node "LED[1]" is assigned to location or region, but does not exist in design Warning: Node "LED[2]" is assigned to location or region, but does not exist in design Warning: Node "LED[3]" is assigned to location or region, but does not exist in design Warning: Node "LED[4]" is assigned to location or region, but does not exist in design Warning: Node "OEN" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[0]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[10]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[11]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[12]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[13]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[14]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[15]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[16]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[17]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[18]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[19]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[1]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[20]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[21]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[22]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[23]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[24]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[25]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[26]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[27]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[28]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[29]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[2]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[30]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[31]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[3]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[4]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[5]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[6]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[7]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[8]" is assigned to location or region, but does not exist in design Warning: Node "PCI_AD[9]" is assigned to location or region, but does not exist in design Warning: Node "PCI_CBEN[0]" is assigned to location or region, but does not exist in design Warning: Node "PCI_CBEN[1]" is assigned to location or region, but does not exist in design Warning: Node "PCI_CBEN[2]" is assigned to location or region, but does not exist in design Warning: Node "PCI_CBEN[3]" is assigned to location or region, but does not exist in design Warning: Node "PCI_CLK" is assigned to location or region, but does not exist in design Warning: Node "PCI_DEVSELN" is assigned to location or region, but does not exist in design Warning: Node "PCI_ENABLEN" is assigned to location or region, but does not exist in design Warning: Node "PCI_FRAMEN" is assigned to location or region, but does not exist in design Warning: Node "PCI_GNTN" is assigned to location or region, but does not exist in design Warning: Node "PCI_IDSEL" is assigned to location or region, but does not exist in design Warning: Node "PCI_INTAN" is assigned to location or region, but does not exist in design Warning: Node "PCI_IRDYN" is assigned to location or region, but does not exist in design Warning: Node "PCI_LOCKN" is assigned to location or region, but does not exist in design Warning: Node "PCI_PAR" is assigned to location or region, but does not exist in design Warning: Node "PCI_PERRN" is assigned to location or region, but does not exist in design Warning: Node "PCI_REQN" is assigned to location or region, but does not exist in design Warning: Node "PCI_RSTN" is assigned to location or region, but does not exist in design Warning: Node "PCI_SERRN" is assigned to location or region, but does not exist in design Warning: Node "PCI_STOPN" is assigned to location or region, but does not exist in design Warning: Node "PCI_TRDYN" is assigned to location or region, but does not exist in design Warning: Node "SC[0]" is assigned to location or region, but does not exist in design Warning: Node "SC[10]" is assigned to location or region, but does not exist in design Warning: Node "SC[11]" is assigned to location or region, but does not exist in design Warning: Node "SC[12]" is assigned to location or region, but does not exist in design Warning: Node "SC[13]" is assigned to location or region, but does not exist in design Warning: Node "SC[14]" is assigned to location or region, but does not exist in design Warning: Node "SC[15]" is assigned to location or region, but does not exist in design Warning: Node "SC[16]" is assigned to location or region, but does not exist in design Warning: Node "SC[17]" is assigned to location or region, but does not exist in design Warning: Node "SC[18]" is assigned to location or region, but does not exist in design Warning: Node "SC[19]" is assigned to location or region, but does not exist in design Warning: Node "SC[1]" is assigned to location or region, but does not exist in design Warning: Node "SC[20]" is assigned to location or region, but does not exist in design Warning: Node "SC[21]" is assigned to location or region, but does not exist in design Warning: Node "SC[22]" is assigned to location or region, but does not exist in design Warning: Node "SC[23]" is assigned to location or region, but does not exist in design Warning: Node "SC[24]" is assigned to location or region, but does not exist in design Warning: Node "SC[25]" is assigned to location or region, but does not exist in design Warning: Node "SC[26]" is assigned to location or region, but does not exist in design Warning: Node "SC[27]" is assigned to location or region, but does not exist in design Warning: Node "SC[28]" is assigned to location or region, but does not exist in design Warning: Node "SC[29]" is assigned to location or region, but does not exist in design Warning: Node "SC[2]" is assigned to location or region, but does not exist in design Warning: Node "SC[30]" is assigned to location or region, but does not exist in design Warning: Node "SC[31]" is assigned to location or region, but does not exist in design Warning: Node "SC[32]" is assigned to location or region, but does not exist in design Warning: Node "SC[33]" is assigned to location or region, but does not exist in design Warning: Node "SC[34]" is assigned to location or region, but does not exist in design Warning: Node "SC[35]" is assigned to location or region, but does not exist in design Warning: Node "SC[36]" is assigned to location or region, but does not exist in design Warning: Node "SC[37]" is assigned to location or region, but does not exist in design Warning: Node "SC[38]" is assigned to location or region, but does not exist in design Warning: Node "SC[39]" is assigned to location or region, but does not exist in design Warning: Node "SC[3]" is assigned to location or region, but does not exist in design Warning: Node "SC[40]" is assigned to location or region, but does not exist in design Warning: Node "SC[4]" is assigned to location or region, but does not exist in design Warning: Node "SC[5]" is assigned to location or region, but does not exist in design Warning: Node "SC[6]" is assigned to location or region, but does not exist in design Warning: Node "SC[7]" is assigned to location or region, but does not exist in design Warning: Node "SC[8]" is assigned to location or region, but does not exist in design Warning: Node "SC[9]" is assigned to location or region, but does not exist in design Warning: Node "SC_CARDSELN" is assigned to location or region, but does not exist in design Warning: Node "SC_CLK1" is assigned to location or region, but does not exist in design Warning: Node "SC_CLK2" is assigned to location or region, but does not exist in design Warning: Node "SC_OSC" is assigned to location or region, but does not exist in design Warning: Node "SC_RESETN" is assigned to location or region, but does not exist in design Warning: Node "S[1]" is assigned to location or region, but does not exist in design Warning: Node "S[2]" is assigned to location or region, but does not exist in design Warning: Node "S[3]" is assigned to location or region, but does not exist in design Warning: Node "S[4]" is assigned to location or region, but does not exist in design Warning: Node "TEMP_CS" is assigned to location or region, but does not exist in design Warning: Node "TEMP_SCK" is assigned to location or region, but does not exist in design Warning: Node "TEMP_SDO" is assigned to location or region, but does not exist in design Warning: Node "USB_CS" is assigned to location or region, but does not exist in design Warning: Node "USB_D[0]" is assigned to location or region, but does not exist in design Warning: Node "USB_D[1]" is assigned to location or region, but does not exist in design Warning: Node "USB_D[2]" is assigned to location or region, but does not exist in design Warning: Node "USB_D[3]" is assigned to location or region, but does not exist in design Warning: Node "USB_D[4]" is assigned to location or region, but does not exist in design Warning: Node "USB_D[5]" is assigned to location or region, but does not exist in design Warning: Node "USB_D[6]" is assigned to location or region, but does not exist in design Warning: Node "USB_D[7]" is assigned to location or region, but does not exist in design Warning: Node "USB_EEDATA" is assigned to location or region, but does not exist in design Warning: Node "USB_PWREN" is assigned to location or region, but does not exist in design Warning: Node "USB_RDN" is assigned to location or region, but does not exist in design Warning: Node "USB_RXFN" is assigned to location or region, but does not exist in design Warning: Node "USB_SK" is assigned to location or region, but does not exist in design Warning: Node "USB_TXEN" is assigned to location or region, but does not exist in design Warning: Node "USB_WR" is assigned to location or region, but does not exist in design Warning: Node "USB_WU" is assigned to location or region, but does not exist in design Warning: Node "V_LCD_ENA" is assigned to location or region, but does not exist in design Warning: Node "V_MEM_ENA" is assigned to location or region, but does not exist in design Warning: Node "V_SC_ENA" is assigned to location or region, but does not exist in design Warning: Node "WEN" is assigned to location or region, but does not exist in design Info: Fitter placement preparation operations beginning Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 Info: Fitter placement operations beginning Info: Starting Vectorless Power Activity Estimation Info: Completed Vectorless Power Activity Estimation Info: Starting Vectorless Power Activity Estimation Info: Completed Vectorless Power Activity Estimation Info: Starting Vectorless Power Activity Estimation Info: Completed Vectorless Power Activity Estimation Info: Fitter placement was successful Info: Fitter placement operations ending: elapsed time is 00:00:03 Info: Estimated most critical path is register to pin delay of 4.247 ns Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X1_Y7; Fanout = 11; REG Node = 'Busy' Info: 2: + IC(1.159 ns) + CELL(0.200 ns) = 1.359 ns; Loc. = LAB_X1_Y7; Fanout = 1; COMB Node = 'ACK_O~9' Info: 3: + IC(0.566 ns) + CELL(2.322 ns) = 4.247 ns; Loc. = PIN_H1; Fanout = 0; PIN Node = 'ACK_O' Info: Total cell delay = 2.522 ns ( 59.38 % ) Info: Total interconnect delay = 1.725 ns ( 40.62 % ) Info: Fitter routing operations beginning Info: Average interconnect usage is 2% of the available device resources. Peak interconnect usage is 4% Info: The peak interconnect region extends from location x0_y0 to location x8_y11 Info: Fitter routing operations ending: elapsed time is 00:00:01 Warning: Following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results Info: Pin CSEL has GND driving its datain port Info: Pin DMACKN has VCC driving its datain port Info: Following groups of pins have the same output enable Info: Following pins have the same output enable: DD[0]~en Info: Type bidirectional pin DD[1] uses the LVTTL I/O standard Info: Type bidirectional pin DD[5] uses the LVTTL I/O standard Info: Type bidirectional pin DD[9] uses the LVTTL I/O standard Info: Type bidirectional pin DD[13] uses the LVTTL I/O standard Info: Type bidirectional pin DD[0] uses the LVTTL I/O standard Info: Type bidirectional pin DD[4] uses the LVTTL I/O standard Info: Type bidirectional pin DD[8] uses the LVTTL I/O standard Info: Type bidirectional pin DD[12] uses the LVTTL I/O standard Info: Type bidirectional pin DD[3] uses the LVTTL I/O standard Info: Type bidirectional pin DD[7] uses the LVTTL I/O standard Info: Type bidirectional pin DD[11] uses the LVTTL I/O standard Info: Type bidirectional pin DD[15] uses the LVTTL I/O standard Info: Type bidirectional pin DD[2] uses the LVTTL I/O standard Info: Type bidirectional pin DD[6] uses the LVTTL I/O standard Info: Type bidirectional pin DD[10] uses the LVTTL I/O standard Info: Type bidirectional pin DD[14] uses the LVTTL I/O standard Info: Quartus II Fitter was successful. 0 errors, 180 warnings Info: Processing ended: Wed Aug 22 00:01:23 2007 Info: Elapsed time: 00:00:19