-- indi16 vhdl
-- Component Declarations
-- (C)2007 K Ring Technologies Semiconductor
-- designed for 66MHz operation

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

PACKAGE indi IS

	COMPONENT alu
		PORT
		(
			ACC, ALU_I				: IN	STD_LOGIC_VECTOR(15 DOWNTO 0);
			ALU_O					: OUT	STD_LOGIC_VECTOR(15 DOWNTO 0);
			C_I						: IN 	STD_LOGIC;
			C_O						: OUT	STD_LOGIC;
			OP						: IN	STD_LOGIC_VECTOR(1 DOWNTO 0)
		);
	END COMPONENT;

	COMPONENT regs
		PORT
		(
			DAT_O					: OUT	STD_LOGIC_VECTOR(15 DOWNTO 0);
			DAT_I					: IN	STD_LOGIC_VECTOR(15 DOWNTO 0);
			CLK_I, WE_I, HLT_I		: IN	STD_LOGIC;
			SD, DRT, RST_I			: IN	STD_LOGIC;
			REG						: IN	STD_LOGIC_VECTOR(1 DOWNTO 0)
		);
	END COMPONENT;
	
	COMPONENT memdrv
		PORT
		(
			-- External Bus Interface
			-- DRAM refreash on PNUL cycles
			Hilo: BUFFER	STD_LOGIC;
			A	: BUFFER	STD_LOGIC_VECTOR(15 DOWNTO 0);
			D	: INOUT	STD_LOGIC_VECTOR(15 DOWNTO 0);
			RW	: OUT	STD_LOGIC;
			
			-- Internal Bus Interface
			CYC		: OUT	STD_LOGIC;
			AR, ARW	: IN	STD_LOGIC_VECTOR(15 DOWNTO 0);
			DR		: OUT	STD_LOGIC_VECTOR(15 DOWNTO 0);
			DRW		: OUT	STD_LOGIC_VECTOR(15 DOWNTO 0);
			DWW		: IN	STD_LOGIC_VECTOR(15 DOWNTO 0);
			RWRW	: IN	STD_LOGIC;
			DRT		: IN	STD_LOGIC;
			SD		: IN	STD_LOGIC;
			PRF		: IN	STD_LOGIC;
			
			-- SoC WISHBONE Classic Interface for all on chip ports
			WBD_I	: IN	STD_LOGIC;
			HLT_I	: IN	STD_LOGIC;
			RST_I	: IN	STD_LOGIC;
			CLK_I	: IN	STD_LOGIC;
			ADR_O	: OUT	STD_LOGIC_VECTOR(15 DOWNTO 0);
			DAT_I	: IN	STD_LOGIC_VECTOR(15 DOWNTO 0);
			DAT_O	: OUT	STD_LOGIC_VECTOR(15 DOWNTO 0);
			WE_O	: OUT	STD_LOGIC;
			SEL_O	: OUT	STD_LOGIC;
			STB_O	: BUFFER	STD_LOGIC;
			ACK_I	: IN	STD_LOGIC;
			CYC_O	: OUT	STD_LOGIC
		);	
	END COMPONENT;
	
	COMPONENT clkpal
		PORT
		(
			CLK_I						: IN	STD_LOGIC;
			Colour, WColour				: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
			Video, HLT_O				: OUT	STD_LOGIC
		);
	END COMPONENT;
	
	COMPONENT dac2
		PORT
		(
			CLK_I				: IN	STD_LOGIC;
			Sample				: IN	STD_LOGIC_VECTOR(15 DOWNTO 0);
			Output				: OUT	STD_LOGIC
		);
	END COMPONENT;
	
END indi;