-- indi16 vhdl
-- Delta Sigma DAC (Second Order)
-- (C)2007 K Ring Technologies Semiconductor
-- designed for 66MHz operation

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY dac2 IS
	PORT
	(
		CLK_I				: IN	STD_LOGIC;
		Sample				: IN	STD_LOGIC_VECTOR(15 DOWNTO 0);
		Output				: OUT	STD_LOGIC
	);
END dac2;

ARCHITECTURE a OF dac2 IS
	SIGNAL Residual, Delay, Diff		: STD_LOGIC_VECTOR(16 DOWNTO 0);
BEGIN
	Diff <= Delay - Residual;
	PROCESS(CLK_I)
		CONSTANT Max		: STD_LOGIC_VECTOR(16 DOWNTO 0) := "10000000000000000";
	BEGIN
		IF rising_edge(CLK_I) THEN
			-- output 1 when +ve and 0 when -ve
			Output <= NOT Diff(16);
			-- calc the residual with sign (assumes +max = 0-(+max) for easier calc)
			-- residual is the overshooted by amount
			Residual <= Max - Diff;
			-- then add anti-phase ultra sonic undershoot (due to delay)
			Delay <= (Sample(15) & Sample) + Residual;
		END IF;
	END PROCESS;
END a;