-- indi16 vhdl
-- ALU
-- (C)2007 K Ring Technologies Semiconductor
-- designed for 66MHz OPeration

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY alu IS
	PORT
	(
		ACC, ALU_I				: IN	STD_LOGIC_VECTOR(15 DOWNTO 0);
		ALU_O					: OUT	STD_LOGIC_VECTOR(15 DOWNTO 0);
		C_I						: IN 	STD_LOGIC;
		C_O						: OUT	STD_LOGIC;
		OP						: IN	STD_LOGIC_VECTOR(1 DOWNTO 0)
	);
END alu;

ARCHITECTURE a OF alu IS
BEGIN
	PROCESS(ACC, ALU_I, C_I, OP)
		VARIABLE Res				:	STD_LOGIC_VECTOR(16 DOWNTO 0);
	BEGIN
		-- full adder
		Res := ('0' & ACC) + ('0' & ALU_I) + ("0000000000000000" & C_I);
		CASE OP IS
			WHEN "00" =>
				ALU_O <= Res(15 DOWNTO 0);
				C_O <= Res(16);
			WHEN "01" =>
				ALU_O <= ACC AND ALU_I;
				C_O <= C_I;
			WHEN "10" =>
				ALU_O <= ACC XOR ALU_I;
				C_O <= C_I;
			WHEN "11" =>
				ALU_O <= ALU_I;
				C_O <= C_I;
		END CASE;
	END PROCESS;
END a;